1. Field of the Invention
This invention relates to testing analog to digital converters and more particularly relates to identifying low error-rate failures in analog to digital converters.
2. Description of the Related Art
An analog to digital converter (“ADC”) is typically tested to assure proper function during operation. For example, a test system is used to introduce a known analog signal to the ADC. The ADC samples the analog signal and converts the analog signal to a digitally encoded instance or digital instance of the analog signal. The test system examines the digital instance to determine if the digital instance represents a value consistent with sampled analog signal.
Testing the ADC is usually successful in identifying repeatable discrepancies between the sampled analog signal and the corresponding value of the converted digital instance. Unfortunately, many anomalies that cause discrepancies between the sampled analog signal and the digital instance—herein referred to as erroneous digitized instances—(“EDI”) may only be occasionally manifest. For example, an EDI caused by noise in the ADC may only occur on average once in a million digital instances. Although a one in a million EDI may be a low error rate, the one in a million error rate may still be sufficiently high to render the ADC unusable for a function. For example, an ADC converting an analog signal from the read head of digital storage device such as a magnetic tape drive to a plurality of digital instances may convert so many digital instances that one in a million EDIs occur regularly and may degrade or render useless the ADC.
Unfortunately, testing an ADC a sufficient number of times to identify low error rate glitches using a test system is prohibitively expensive. Test systems for testing ADCs, particularly test systems for semiconductor ADCs, are expensive and each second of test time is a significant cost. A test system testing an ADC for a sufficient amount of time to identify low error rate EDIs by inputting a known analog signal and testing the output digitized instance of the analog signal may significantly increase the cost of the ADC. For example, inputting and testing the five million (5,000,000) analog signal/digitized instance pairs in order to accurately identify an ADC with a target error rate of two in ten million EDIs may require several seconds test system time for each ADC, greatly increasing test costs particularly if multiple ADCs must be tested on a semiconductor die.
From the foregoing discussion, it should be apparent that a need exists for an apparatus, system, and method for hardware-based testing for low error rate EDIs in an ADC. Beneficially, such an apparatus, system, and method would reduce the cost and increase the reliability of ADCs.